The present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention relates to techniques for detecting faults that may occur during operation of an integrated circuit device such as a processor.
As integrated circuit (IC) fabrication technology improves, manufacturers are able to integrate additional functionality onto a silicon substrate. As the number of these functionalities increases, however, so does the number of components on an IC chip. Additional components add additional signal switching, in turn, generating more heat. The additional heat may damage an IC chip by, for example, thermal expansion. Also, the additional heat may limit usage locations and/or applications of a computing device that includes such chips.
To reduce such shortcomings (and possibly improve performance), some implementations may decrease the process size and/or the operating voltage of an IC chip. However, reduction in process size and voltage may make IC devices more susceptible to transient failures. In response, some processors may utilize various techniques for protection against transient errors, such as error correction code (ECC), redundant multithreading, or redundant circuitry. Implementing such solutions may however result in an increase in area, increase in power consumption, and/or increase in performance overheads that may render such solutions impractical.